Zeolite - carbon doped oxide composite low k dielectric

ABSTRACT

A method for forming a zeolite-carbon doped oxide (CDO) composite dielectric material is herein described. Zeolite particles may be dispersed in a solvent. The zeolite solvent solution may then be deposited on an underlying layer, such as a wafer or other dielectric layer. At least some solvent may then be removed to form a zeolite film. A CDO may then be deposited in the zeolite film to form a zeolite-CDO composite film/dielectric. The Zeolite-CDO composite film/dielectric may then be calcinated to form a solid phase zeolite-CDO composite dielectric.

This application is a Divisional of U.S. patent application Ser. No. 10/716,250, entitled “Zeolite-Carbon Doped Oxide composite Low K Dielectric,” by Hai Deng, filed on Nov. 17, 2003. This invention relates to the field of fabricating semiconductor devices and, in particular, to composite low k dielectrics.

FIELD Background

Modern integrated circuits generally contain several layers of interconnect structures fabricated above a substrate. The substrate may have active devices and/or conductors that are connected by the interconnect structure.

Interconnect structures, typically comprising trenches and vias, are usually fabricated in, or on, an interlayer dielectric (ILD). It is generally accepted that, the dielectric material in each ILD should have a low dielectric constant (k) to obtain low capacitance between conductors. Decreasing this capacitance between conductors, by using a low dielectric constant (k), results in several advantages. For instance, it provides reduced RC delay, reduced power dissipation, and reduced cross-talk between the metal lines.

Materials commonly used to achieve low k dielectrics/films are carbon doped oxides (CDOs) or amorphous CDOs. CDOs tend to have a k value less than 3.5, but suffer from weak mechanical properties. These weak mechanical properties often result in cracking of the CDO during high stress processing and packaging steps.

Another material that may be potentially used for ILDs is zeolite or silica zeolite. Zeolite material is advantageous in that they have high porosity and a relatively uniform pore distribution. Zeolite material also is known to have good mechanical strength. Furthermore, zeolite films have dielectric constants in the range of 2.7 and smaller. Yet, zeolite is a crystalline structure, which makes forming a uniform film extremely difficult.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not intended to be limited by the figures of the accompanying drawings.

FIG. 1 illustrates a solution with zeolite particles dispersed in the solvent.

FIG. 2 is a cross-sectional elevation view of an underlying layer with a conductor and an etch stop disposed on the underlying layer.

FIG. 3 is a cross-sectional elevation view of the solution from FIG. 1 after it has been deposited on the underlying layer from FIG. 2 and at least some of the solvent has been removed to form a zeolite film.

FIG. 4 is a cross-sectional elevation view of FIG. 3 after a carbon doped oxide precursor has been deposited in the porous zeolite film to form a zeolite-CDO film.

FIG. 5 is a cross-sectional elevation view of FIG. 4 after the zeolite-CDO film has been calcinated.

FIG. 6 is a cross-sectional elevation view of FIG. 5 after a via opening and a trench have been etched.

FIG. 7 is a cross-sectional elevation view of FIG. 6 after a barrier layer has been deposited on the surfaces of the zeolite-CDO film and a conductive material has been formed in the via opening and the trench.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth such as examples of specific solvents, deposition methods, carbon doped oxides, etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known methods and materials, such as spin-coating, dip-coating, and zeolite nano-particle preparation have not been described in detail in order to avoid unnecessarily obscuring the present invention.

The method and interconnect structure described herein are for forming interlayer dielectrics (ILDs) from a zeolite-carbon doped oxide (CDO) composite. A composite may be any combination of two or more materials, such as a carbon doped oxide and zeolite, whether actual bonds are present or not. A composite may also be a material formed from a combination of materials which differ in composition or form and retain their identities and properties. A composite may also include a nano-composite, where the zeolite particles are nano sized.

Referring to FIG. 1, a solvent-zeolite solution 115 is depicted. Solvent-zeolite solution 115 may be any suspension, mixture, solution, or colloid comprising solvent 105 and zeolite particles 110. Zeolite particles 110 are dispersed in solvent 105. Solvent 105 may be any low molecular solvent, such as water, or solvent 105 may be any organic oligomer, such as polyethylene glycol, poly styrene, poly (Methacrylates), Poly (acrylate), poly ethylene oxide, or any other organic oligormer. Zeolite particles 110 may be dispersed in solvent 105 by adding them to solvent 105. Furthermore, zeolite particles 110 may be may be dispersed in solvent 105 by stirring both zeolite particles 110 and solvent 105. For example, zeolite particles 110 may be dispersed/stirred into solvent 105 by putting the solution in a centrifuge and spinning solvent 105 until zeolite particles 110 are suspended in solvent-zeolite solution 115.

Zeolite particles 105 may be any size particles including nano-sized particles. Nano-sized zeolite particles may be obtained by spinning a zeolite-solvent solution at low speeds to separate out the large zeolite particles. Furthermore, the amount of zeolite particles 110 may be varied to obtain different zeolite concentration in the solvent-zeolite solution 115, as well as the properties of the final zeolite-carbon doped oxide composite, which is discussed later in reference to FIGS. 4-7.

Turning to FIG. 2, and underlying layer 205 is depicted, which often is comprised of several active devices and/or a layer with conductors exposed. Underlying layer 205 may be a semiconductor wafer including device regions, other structures such as gates, local interconnects, metal layers, or other active/passive device structures or layers.

In FIG. 2, underlying layer 205 has underlying conductor 210. Underlying conductor 210 may be copper or copper alloy, as well as some other conductive material such as gold. Underlying layer 205 may also be a carbon doped oxide-zeolite composite dielectric in accordance with this disclosure, which may contain any of the aforementioned devices. An etch stop 215 is disposed on underlying layer 205, which may be comprised of silicon nitride (Si3N4), silicon carbide (SiC), or any other etch resistant material.

FIG. 3 illustrates a zeolite film 310 disposed on underlying layer 205 after a zeolite-solvent solution, such as zeolite-solvent solution 115 as shown in FIG. 1, has been deposited on underlying layer 205 and at least some of the solvent has been removed in step 305. Step 305 may include deposition of a zeolite-solvent solution. Deposition of a zeolite-solvent solution may include any variety of known methods for deposition of materials in semiconductor fabrication. For example, the zeolite-solvent solution may be deposited by dip-coating underlying layer 205 in the zeolite-solvent solution. As another example, the zeolite-solvent solution may be deposited by spin-coating the zeolite-solvent solution on underlying layer 205. It is readily apparent that these well-known methods, as well as other well-known methods, of depositing dielectric material may be used to deposit the solvent solution on underlying layer 205.

Furthermore, step 305 may include removing at least some of the solvent from the zeolite-solvent solution to form zeolite film 310. Removing at least some of the solvent may include drying the zeolite-solvent solution to remove at least some of the solvent. For example, drying may be done in air or by vacuum.

FIG. 4 illustrates zeolite-carbon doped oxide (CDO) composite film 415 disposed on underlying layer 205, after a CDO has been deposited in a zeolite film, such as zeolite film 310 shown in FIG. 3, in step 405. As an example CDO 410 may be silicon oxide, (SiC_(x)O_(y)H_(z)), or any other CDO. Step 405 may be any process where CDO 410 is deposited in a zeolite film. As an illustrative example of CDO deposition process 405, CDO 410 may be deposited in a zeolite film by chemical vapor deposition.

As shown in FIG. 5, after CDO 410 is deposited, the zeolite-CDO may be re-flowed and calcinated, such as in calcinations process 505. Calcination process 505 may form a zeolite-CDO composite dielectric/film, such as zeolite-CDO composite dielectric layer 510. Step 505 may be any process where the zeolite-CDO composite film 415, as shown in FIG. 4, is heated and cooled to form zeolite-CDO composite dielectric layer 510, shown if FIG. 5.

For example, calcination process 505 may include heating zeolite-CDO composite film 415. As a specific example, zeolite-CDO composite film 415 may be heated at an ambient temperature in the range of 300° C. to 550° C. for an amount of time. Heating may be done in oven, furnace, or any other device for heating interconnect structures. Heating may also cause the CDO components of zeolite-CDO composite film 415 to reflow and form a continuous matrix. Calcination process 505 may also include oxidizing zeolite-CDO composite film 415. Oxidizing zeolite-CDO composite film 415 may include allowing the air to oxidize zeolite-CDO composite film 415 over a period of time or exposing the structure to an induced ozone. Moreover, calcination process 505 may also include vacuuming to remove any side-product from zeolite-CDO composite film 415.

It is readily apparent that each of the methods of removing liquid from zeolite-CDO composite film 415 may individually or combinationally be used to extract at least some liquid from zeolite-CDO composite film 415. As an illustrative example, zeolite-CDO composite film 415 may be heated in an oven while under a vacuum. Calcination process 505 may also include cooling zeolite-CDO composite film 415, after heating, to form layer 510 and freeze layer 510 into a solid form. Cooling may include allowing layer 510 to cool at room temperature for an amount of time at a variable cooling rate. Cooling may also include refrigeration within a refrigerator or other cooling device to cool layer 510.

As shown in FIG. 6 and FIG. 7, further damascene processing may be done on the zeolite-CDO composite dielectric layer 510. In FIG. 6, a via opening 605 and a trench 610 is etched in zeolite-CDO composite dielectric layer 510. In FIG. 7, a barrier layer 705 is deposited on the surfaces of zeolite-CDO composite dielectric layer 510. Then conductive material 710 is formed in via opening 605 and trench 610. It is apparent that other well-known steps, such as chemical mechanical polish (CMP) and materials, such as copper, tantalum, etc., in the damascene process have been left out so as not to obscure the discussion of zeolite-CDO composite material.

Therefore, as discussed above a composite zeolite-CDO dielectric layer/film may be created that has the low k dielectric constant and is able to form a uniform layer. The composite zeolite-CDO dielectric may have greater mechanical strength than a CDO film, because of the addition of zeolite. Furthermore, instead of the non-uniform film that is usually created with pure zeolite films, a uniform film may be created with the introduction of a CDO material into the composite.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. 

1.-24. (canceled)
 25. An interconnect structure comprising: at least a via opening and a trench opening defined by a carbon doped oxide (CDO)-zeolite composite dielectric layer, which is disposed above an underlying layer; a barrier layer disposed on the surfaces of the carbon doped oxide (CDO)-zeolite composite dielectric layer; and conductive material disposed in the via opening and the trench opening.
 26. The interconnect structure of claim 25, wherein the CDO is a silicon oxide.
 27. The interconnect structure of claim 25, wherein the barrier layer comprises tantalum.
 28. The interconnect structure of claim 25, wherein the conductive material comprises a copper alloy.
 29. The interconnect structure of claim 25, wherein the underlying layer is a wafer.
 30. The interconnect structure of claim 25, wherein the underlying layer includes a second CDO-zeolite composite dielectric layer.
 31. An interconnect structure comprising: a first dielectric layer including a carbon doped oxide (CDO)-zeolite composite material, wherein a conductive material is disposed in an opening of the first dielectric layer; and a second dielectric layer including a CDO-zeolite composite material disposed on the first dielectric layer, wherein a conductive material is disposed in an opening of the second dielectric layer; the conductive material disposed in the opening of the second dielectric to make electrical connection with the conductive material disposed in the opening of the first dielectric layer.
 32. The interconnect structure of claim 31, wherein the conductive material includes a copper alloy.
 33. The interconnect structure of claim 31, further comprising a first barrier layer disposed between the conductive material, which is disposed in an opening of the first dielectric layer, and surfaces of the first dielectric layer; and a second barrier layer disposed between the conductive material, which is disposed in an opening of the second dielectric layer, and the surfaces of the second dielectric layer.
 34. The interconnect structure of claim 33, wherein the barrier layer includes tantalum.
 35. The interconnect structure of claim 31, wherein the first and the second dielectric layers are disposed above an underlying active substrate layer. 